Add MIPS support to pixelflinger.
See the comment-block at the top of MIPSAssembler.cpp for
implementation overview.
Change-Id: Id492c10610574af8c89c38d19e12fafc3652c28a
diff --git a/libpixelflinger/codeflinger/CodeCache.cpp b/libpixelflinger/codeflinger/CodeCache.cpp
index a713feb..4f2ede3 100644
--- a/libpixelflinger/codeflinger/CodeCache.cpp
+++ b/libpixelflinger/codeflinger/CodeCache.cpp
@@ -36,6 +36,12 @@
#include <errno.h>
#endif
+#if defined(__mips__)
+#include <asm/cachectl.h>
+#include <errno.h>
+#endif
+
+// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
Assembly::Assembly(size_t size)
@@ -155,12 +161,12 @@
mCacheInUse += assemblySize;
mWhen++;
// synchronize caches...
-#if defined(__arm__)
+#if defined(__arm__) || defined(__mips__)
const long base = long(assembly->base());
const long curr = base + long(assembly->size());
err = cacheflush(base, curr, 0);
- ALOGE_IF(err, "__ARM_NR_cacheflush error %s\n",
- strerror(errno));
+ ALOGE_IF(err, "cacheflush error %s\n",
+ strerror(errno));
#endif
}