Chris Dearman | 52998578 | 2013-12-06 04:29:37 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | /* |
| 18 | * Dwarf2 data encoding flags. |
| 19 | */ |
| 20 | |
| 21 | #define DW_EH_PE_absptr 0x00 |
| 22 | #define DW_EH_PE_omit 0xff |
| 23 | #define DW_EH_PE_uleb128 0x01 |
| 24 | #define DW_EH_PE_udata2 0x02 |
| 25 | #define DW_EH_PE_udata4 0x03 |
| 26 | #define DW_EH_PE_udata8 0x04 |
| 27 | #define DW_EH_PE_sleb128 0x09 |
| 28 | #define DW_EH_PE_sdata2 0x0A |
| 29 | #define DW_EH_PE_sdata4 0x0B |
| 30 | #define DW_EH_PE_sdata8 0x0C |
| 31 | #define DW_EH_PE_signed 0x08 |
| 32 | #define DW_EH_PE_pcrel 0x10 |
| 33 | #define DW_EH_PE_textrel 0x20 |
| 34 | #define DW_EH_PE_datarel 0x30 |
| 35 | #define DW_EH_PE_funcrel 0x40 |
| 36 | #define DW_EH_PE_aligned 0x50 |
| 37 | #define DW_EH_PE_indirect 0x80 |
| 38 | |
| 39 | /* |
| 40 | * Dwarf2 call frame instructions. |
| 41 | */ |
| 42 | |
| 43 | typedef enum { |
| 44 | DW_CFA_advance_loc = 0x40, |
| 45 | DW_CFA_offset = 0x80, |
| 46 | DW_CFA_restore = 0xc0, |
| 47 | DW_CFA_nop = 0x00, |
| 48 | DW_CFA_set_loc = 0x01, |
| 49 | DW_CFA_advance_loc1 = 0x02, |
| 50 | DW_CFA_advance_loc2 = 0x03, |
| 51 | DW_CFA_advance_loc4 = 0x04, |
| 52 | DW_CFA_offset_extended = 0x05, |
| 53 | DW_CFA_restore_extended = 0x06, |
| 54 | DW_CFA_undefined = 0x07, |
| 55 | DW_CFA_same_value = 0x08, |
| 56 | DW_CFA_register = 0x09, |
| 57 | DW_CFA_remember_state = 0x0a, |
| 58 | DW_CFA_restore_state = 0x0b, |
| 59 | DW_CFA_def_cfa = 0x0c, |
| 60 | DW_CFA_def_cfa_register = 0x0d, |
| 61 | DW_CFA_def_cfa_offset = 0x0e |
| 62 | } dwarf_CFA; |
| 63 | |
| 64 | /* |
| 65 | * eh_frame_hdr information. |
| 66 | */ |
| 67 | |
| 68 | typedef struct { |
| 69 | uint8_t version; |
| 70 | uint8_t eh_frame_ptr_enc; |
| 71 | uint8_t fde_count_enc; |
| 72 | uint8_t fde_table_enc; |
| 73 | uintptr_t eh_frame_ptr; |
| 74 | uint32_t fde_count; |
| 75 | } eh_frame_hdr_info_t; |
| 76 | |
| 77 | /* |
| 78 | * CIE information. |
| 79 | */ |
| 80 | |
| 81 | typedef struct { |
| 82 | uint8_t version; |
| 83 | uint32_t code_align; |
| 84 | uint32_t data_align; |
| 85 | uint32_t reg; |
| 86 | uint32_t aug_z; |
| 87 | uint8_t aug_L; |
| 88 | uint8_t aug_R; |
| 89 | uint8_t aug_S; |
| 90 | uint32_t aug_P; |
| 91 | } cie_info_t; |
| 92 | |
| 93 | /* |
| 94 | * FDE information. |
| 95 | */ |
| 96 | |
| 97 | typedef struct { |
| 98 | uint32_t start; |
| 99 | uint32_t length; // number of instructions covered by FDE |
| 100 | uint32_t aug_z; |
| 101 | uint32_t aug_L; |
| 102 | } fde_info_t; |
| 103 | |
| 104 | /* |
| 105 | * Dwarf state. |
| 106 | */ |
| 107 | |
| 108 | /* Stack of states: required for DW_CFA_remember_state/DW_CFA_restore_state |
| 109 | 30 should be enough */ |
| 110 | #define DWARF_STATES_STACK 30 |
| 111 | |
| 112 | typedef struct { |
| 113 | char rule; // rule: o - offset(value); r - register(value) |
| 114 | uint32_t value; // value |
| 115 | } reg_rule_t; |
| 116 | |
| 117 | /* Dwarf preserved number of registers for mips */ |
| 118 | typedef enum |
| 119 | { |
| 120 | UNW_MIPS_R0, |
| 121 | UNW_MIPS_R1, |
| 122 | UNW_MIPS_R2, |
| 123 | UNW_MIPS_R3, |
| 124 | UNW_MIPS_R4, |
| 125 | UNW_MIPS_R5, |
| 126 | UNW_MIPS_R6, |
| 127 | UNW_MIPS_R7, |
| 128 | UNW_MIPS_R8, |
| 129 | UNW_MIPS_R9, |
| 130 | UNW_MIPS_R10, |
| 131 | UNW_MIPS_R11, |
| 132 | UNW_MIPS_R12, |
| 133 | UNW_MIPS_R13, |
| 134 | UNW_MIPS_R14, |
| 135 | UNW_MIPS_R15, |
| 136 | UNW_MIPS_R16, |
| 137 | UNW_MIPS_R17, |
| 138 | UNW_MIPS_R18, |
| 139 | UNW_MIPS_R19, |
| 140 | UNW_MIPS_R20, |
| 141 | UNW_MIPS_R21, |
| 142 | UNW_MIPS_R22, |
| 143 | UNW_MIPS_R23, |
| 144 | UNW_MIPS_R24, |
| 145 | UNW_MIPS_R25, |
| 146 | UNW_MIPS_R26, |
| 147 | UNW_MIPS_R27, |
| 148 | UNW_MIPS_R28, |
| 149 | UNW_MIPS_R29, |
| 150 | UNW_MIPS_R30, |
| 151 | UNW_MIPS_R31, |
| 152 | |
| 153 | UNW_MIPS_PC = 34, |
| 154 | |
| 155 | /* FIXME: Other registers! */ |
| 156 | |
| 157 | /* For MIPS, the CFA is the value of SP (r29) at the call site in the |
| 158 | previous frame. */ |
| 159 | UNW_MIPS_CFA, |
| 160 | |
| 161 | UNW_TDEP_LASTREG, |
| 162 | |
| 163 | UNW_TDEP_LAST_REG = UNW_MIPS_R31, |
| 164 | |
| 165 | UNW_TDEP_IP = UNW_MIPS_R31, |
| 166 | UNW_TDEP_SP = UNW_MIPS_R29, |
| 167 | UNW_TDEP_EH = UNW_MIPS_R0 /* FIXME. */ |
| 168 | |
| 169 | } |
| 170 | mips_regnum_t; |
| 171 | |
| 172 | #define DWARF_REGISTERS UNW_TDEP_LASTREG |
| 173 | |
| 174 | typedef struct { |
| 175 | uintptr_t loc; // location (ip) |
| 176 | uint8_t cfa_reg; // index of register where CFA location stored |
| 177 | intptr_t cfa_off; // offset |
| 178 | reg_rule_t regs[DWARF_REGISTERS]; // dwarf preserved registers for mips |
| 179 | } dwarf_state_t; |
| 180 | |
| 181 | /* DWARF registers we are caring about. */ |
| 182 | |
| 183 | |
| 184 | #define DWARF_SP UNW_MIPS_R29 |
| 185 | #define DWARF_RA UNW_MIPS_R31 |
| 186 | #define DWARF_PC UNW_MIPS_PC |
| 187 | #define DWARF_FP UNW_MIPS_CFA /* FIXME is this correct? */ |